Multi-algorithm ASIP synthesis and power estimation for DSP applications

Power consumption is an increasingly important parameter in the design of mixed hardware/software systems. This work applies the high-level synthesis technique to multi-algorithms and explores its use as a means of analyzing power consumption from the high level of design. We apply a multi-algorithm synthesis technique to designing an application specific instruction set processor (ASIP) from a customized ASIC. This technique synthesizes selected time constrained algorithms to define a set of DSP applications, designs the corresponding ASIP core, and extracts the specific instruction set. Although not as effective as a DSP core solution, this technique provides much of the circuit flexibility while maintaining an available trade-off between performance and power dissipation. This technique contains three power estimators to assist algorithm integration with the view to optimizing the embedded system: the first acts during the application of usual high-level synthesis steps. The second one is triggered after the complete synthesis of the target algorithm, and the third estimator is based on the instruction set of the designed ASIP core. This technique has been implemented in our framework called BSS (Breizh Synthesis System).