Design of 1 V switched-current cells in standard CMOS process

The minimum supply voltage for a typical switched-current (SI) cell can be shown to be greater than 2V/sub T/+2V/sub DSsat/ approximately due to the fact that an additional voltage drop is required for the MOS switch, which is connected to the gate of the memory transistor. Thus, a minimum supply voltage of 1.5 V is usually required in a standard CMOS process. In this paper, an active switching scheme is proposed for designing SI cells. The minimum supply voltage is equal to V/sub T/+2V/sub DSsat/. As a result, 1 V SI cells that exhibit low charge injection errors can be achieved.