Comparison of Impedance Measurement Techniques for Extracting Parasitic Inductance of SiC MOSFETs

The parasitic inductances of silicon carbide (SiC) MOSFETs have a significant influence on device performance, and limit the switching frequency and power density in practical applications. This paper compares three different inductance extraction techniques for SiC MOSFETs: the one-port impedance (Z-parameter) measurement with the third terminal floating, the one-port Z-parameter measurement with the third terminal shorted, and the two-port scattering (S) parameters measurement. These three extraction methods are compared analytically, experimentally, and with Advanced Design System (ADS) high frequency circuit simulation. It is found that the one-port floating terminal method introduces the highest measurement errors and uncertainty, which can be somewhat improved by shorting the floating terminal to the ground. However, the two-port method offers the best measurement accuracy, and remains as the only approach applicable to power modules with more than three terminals.