Enhancing the Parallelization of Backpropagation Neural Network Algorithm for Implementation on FPGA Platform

Backpropagation Neural Network Algorithm is a long-standing supervised algorithm, with applications in many domains. This method is useful when there is a predefined set of input and output vectors, and aiming to produce the output for the given input. However, to reduce the computational time latency, many optimization techniques that are available in Vivado HLS tool were applied to generate a downable code for FPGA platform to enhance the performance of the algorithm. The overall latency has been reduced from 3.44ms without optimization to 2.42ms with optimization. Therefore, the latency reduced by about 1.4 times. This paper also implemented and paralyzed the same algorithm on CPU and GPU for comparison purposes. The result shows the FPGA implementation gives better results than CPU and GPU on the comparison of performance due to the applied optimization techniques in the implementation.