Back-End Electronics Based on an Asymmetric Network for Low Background and Medium- Scale Physics Experiments

The detector readout architecture introduced in this paper is intended for small to medium size physics experiments that have moderate bandwidth needs and applications that only tolerate an ultimately low background radioactivity for the parts close to the detector. The first idea to simplify the readout system and minimize the material budget is to use a common fan-out structure to transport from off-detector back-end electronics to the front ends all the traffic required for the synchronization, configuration, and readout. The second idea is to use between each front-end card and the back-end electronics a point-to-point link that runs at the relatively low speed that suffices for the target application. This broadens the possible choices of physical media, e.g., glass fiber, plastic optical fiber, or copper. This paper presents a communication protocol adequate for the proposed asymmetric network. It shows the design of a back-end unit capable of controlling 32 front-end units at up to 12.8 Gb/s of aggregate bandwidth. This back-end unit uses an inexpensive commercial field-programmable gate array (FPGA) module where a large number of regular I/O pins interface to the front-end links, while the few available multigigabit per second capable transceivers are assigned to the communication with the upper stage of the data acquisition (DAQ) system.