Dynamic-Reference-Voltage-based Detection Algorithm for LDPC-Coded NAND Flash Memory

In flash memory, the overlap region between the threshold-voltage distributions of two adjacent storage states becomes larger with the program/erase (P/E) cycles and retention time, which dramatically degrades the storage reliability. To address the above problem, we propose a novel dynamic-reference-voltage-based detection algorithm for LDPC-coded NAND flash memory with both cell-to-cell interference (CCI) and retention noise. Specifically, we first employ Monte-Carlo simulations to analyze the threshold voltages of each storage state, and find that these threshold voltages can be approximately characterized by a Gaussian distribution. According to such a distribution, we further develop a dynamic modification scheme for the reference voltages, which can efficiently update the initial likelihood ratio (LLR) for the LDPC decoder. Experimental results illustrate that the proposed detection algorithm not only can achieve significant performance gain over other existing counterparts, but also can remarkably increase the overall P/E cycles and retention time. Thanks to the aforementioned superiorities, the proposed detection algorithm appears to be an excellent alternative to other counterparts for future high-density flash memory.