Evaluation of 3D & 4D Two Layer Mesh NoC for Fault Tolerance over Combinations of Vertical Channel

There can be failure of on-chip interconnects at GHz frequencies, which are implemented using submicron technology. Also the failures increase with extreme device scaling. Three dimensional (3D) Networks on Chips (NoCs) implemented using 3D-mesh topology makes use of TSVs to increase the communication Bandwidth. This further increases the risk of failure of chips at the time of fabrication and runtime. Hence, for better field and reliability, it require having efficient and effective methods to improve the fault tolerance. In this paper modeled the equilibrium number of packets of NoC over vertical channels. These vertical channels are placed over virtual sphere over mesh topology. Also derived the objective function for the latency calculation over packets switch network in a mesh NoC. Proposed here spatially spaced sphere based vertical channel scheme for 3D & 4D NoCs. This scheme is tested to support fault tolerance network with various percentage of break in mesh topology links from 10%-50 % to demonstrate reliability and yield. We demonstrated the performance evaluation matrix over throughput and latency for 2 layers 18×18 3D & 4D NoC over FTP and CBR applications. Also proposed the adaptive XYZ routing algorithms in support of the proposed scheme.