Design of Low Power High Speed SRAM Architecture using SK-LCT Technique

In many VLSI chips, Static Random Access memory (SRAM) has become an important part due to their large storage capacity and small access time. Low power adequate memory design is one of the most challenging issues in SRAM architecture. As the technology node scaling down, leakage power consumption has become a significant problem. There are various power gating schemes available in the literature such as sleep technique, stack technique, sleepy stack technique, sleepy keeper technique, lector technique, foot switch technique and double switch technique for leakage power reduction. In this paper a novel power gating technique namely sleepy keeper leakage control transistor technique (SK-LCT) is proposed for a low power SRAM architecture design. The SRAM architecture has two main components, namely SRAM cell and sense amplifier. The proposed SK-LCT technique is applied in both SRAM cell and sense amplifier for a new low power high speed SRAM architecture design. Simulation is done using Tanner EDA tool in 180nm technology and the results obtained show a significant improvement in leakage power consumption and speed.