Cu pillar as interconnect for 10 μm pitch and below: Fabrication issues and assembly results

This paper describes an interconnect technology based on copper pillar for the assembly of Si on Si die at a 10 μm pitch and format as large as 1cm
²
. Slowly some technologies are being developed at this pitch, especially in some niche application. They involve In based solder or micro-tube insertion at room temperature or micro-insert. Even if these technologies present some advantages, the supply chain does not exist in the main OSAT which is one reason for investigating copper pillar. The first part of the study describes the fabrication process issues and how to solve them. Some vehicle tests are fabricated and the diameter is measured at several places in the wafer to validate the photoresist resolution. Two resists are used, one with a good resolution giving diameter within 0.2 μm of the drawn diameter but with systematic residues at the foot of the pillar, and a second one which systematically overestimate the diameter by 1 μm but with straight wall. The fabricated Cu/Ni/SnAg pillars present a good height uniformity over 90% per chip and per wafer. Finally some assembly using two different processes are developed and achieves 100% connections, with contact resistance within expectation, and shear values ranging from 93MPa to 155MPa.