Utilizing Thermo-Mechanical CPI Simulation to Define a 7nm Package Envelope

The objective of this work is to use simulation results of a back end of line (BEOL) construction known to be susceptible to white bump failure to predict Chip package interaction (CPI) failure risk of other designs, prior to running a reliability qualification. This learning is applied to new 7nm chip and package configurations for a wide range of design points. Key attributes include bump pattern, core versus coreless substrate effects, use of a jig during the reflow process, different substrate prepeg materials, impact of additional TEOS dielectric layers in the BEOL stack, and different die thicknesses. Simulations were carried out using the structural analysis module - Ansys Mechanical
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. Thermal boundary conditions were applied to mimic the chip reflow process. The simulation methodology predicted the lowest CPI risk for a 7nm qualification. An optimized package with a lower CTE substrate, additional TEOS layers and a thicker die was found to be the best case scenario with respect to white bump risk.