Simulation Analysis of InAlN/GaN Monolithic NAND Logic Cell

This paper presents simulation analysis of monolithic integrated InAlN/GaN NAND logic cell comprised of depletion-mode and dual-gate enhancement-mode high electron mobility transistors. Calibrated static and dynamic electrophysical models are proposed for 2-D device simulations in Sentaurus Device environment. Circuit models of both transistors are designed and calibrated by experimental results and 2-D device simulations.