A −40 dB EVM, 77 MHz Dual-Band Tunable Gain Sub-Sampling Receiver Front End in 65-nm CMOS

In this paper, the first dual-band sub-sampling receiver front end with sampling frequency optimization to meet the ultimate receiver error vector magnitude (EVM) of -40 dB over wide input power range of 19 dB is proposed. A systematic sub-sampling receiver chain EVM optimization with respect to major system-level impairments, such as noise folding, sampling frequency, IQ mismatches, phase noise of the sub-sampling clock, and unit capacitor value realizable at the decimation filter, is presented. The proposed dual-band sub-sampling receiver has a 26-41 dB continuously tunable gain for 2.4 GHz and 26-38.5 dB for the 5 GHz WLAN band. Continuously tunable gain ensures the ultimate receiver EVM performance over wider input power levels. In addition, the 5 GHz band is continuously tunable from 4.5 to 5.7 GHz. An active balun feedback low-noise amplifier followed by a sub-sampling down-conversion mixer is implemented to down-convert both WLAN bands to an intermediate frequency in the range from 445 to 538 MHz. Sub-sampling frequency optimization proposed in this paper down-converts both WLAN bands with the sampling frequency from 1.78 to 2.15 GHz to reach the target EVM. Additionally, a switched capacitor decimation filter running at 90 MHz is implemented to provide dual functionalities of down-conversion to baseband and band selection. A test-chip is implemented in a 1.2 V 65-nm CMOS technology. The proposed dual-band sub-sampling receiver occupies a total active area of 0.72 mm
²
and has a total power dissipation of 55.6 mW. The overall receiver chain shows a noise figure of 11.5 dB at the highest gain and an IIP3 of -8 dBm at the lowest gain.