When should on-chip inductance modeling become necessary for VLSI timing analysis?

Copper-based 0.13 /spl mu/m technologies targeting System-on-a-Chip (SoC) are becoming available for VLSI designs, while aluminum-based 0.18 /spl mu/m and 0.25 /spl mu/m technologies are being used by main-stream, high-end VLSI design groups. Besides material change and technology scaling, other factors that make on-chip inductance modeling become more important are: integration level, harmonic frequency, design style, et al. In essence, many process and layout parameters of today's VLSI designs can have potentially first-order effects on how much inductance modeling affects the timing of a critical net. In this paper, our research result indicate the most critical parameters are material property, process feature size, interconnect length, and driver size. We use typical but critical signal nets in VLSI chips, model them by 3-D RLC extractor, and simulate them by SPICE. This methodology can help identify a proper subset of nets that require detailed RLC-based timing analysis. In this way, more efficient timing analysis without considering inductance modeling (e.g. for SoC) can be performed for other nets.