Optimisation and Simulation of RC Time Constants in Snubber Circuits

Semiconductor devices are subjected to elevated levels of stresses when used at high voltage high current and temperature applications. This stress is mainly due to hard switching which is proportional to the switching frequency. This paper presents methods used to remove this energy to prevent expensive switch damage due to overheating and high dv/dt oscillations. In confirmation of the research title, the process in the determination of `RC' in snubber circuits has been proven by OrCAD optimisation and presented.