Design and Analysis of Novel Interconnects with Network-on-Chip LVDS Transmitter for Low Delay

In this paper, a novel global interconnect low voltage differential signaling (LVDS) transmitter for network-on-chip (NOC) has been proposed to achieve less global interconnect delay and low power dissipation. The proposed interconnect with transmitter has been examined in two different conditions, without buffer and with buffer in between interconnect and also impact of feature size scaling has been analyzed. The performance has been analyzed for the NOC interconnect with 0.350 μm and 0.180 μm CMOS technology. On scaling the technology with 0.350 μm to 0.180 μm, the results show 15.68% global interconnect delay reduce for transmitter without buffer (Model-I) in between interconnect and with buffer (Model-II) global interconnect delay reduction of 15.83%. A significant reduction in power dissipation is achieved by selecting a proper sizing of transistor and using differential signaling technique of the data transmission. The power dissipation in 0.350 μm technology is 1.78 mW and 0.180 μm technology is 2.1929 mW, respectively, at data rate of 2.9 Gbps and 3.5 Gbps at different technology for two different models.