A Configurable RISC-V for NoC-Based MPSoCs: A Framework for Hardware Emulation

Manycore architectures with thousands of processing tiles create interesting challenges to maintain high processing speeds with satisfiable energy dissipation. One of these architectures, Networks-on-Chips (NoC) proved to be a suitable candidate to achieve that target goal. In this paper, we introduce a highly scalable, flexible hardware RISC-V MPSoC-based NoC hardware emulation and testbench acceleration co-modeling framework through which NoCs, built upon various types of network schemes can be validated and evaluated. In our proposed platform, traffic is injected or self-generated through the open source RISC-V Instruction Set Architecture (ISA) as a processing tile through an implemented Core Network Interface (CNI), which acts as an NI-plugin. Hardware emulation environment has been developed to be auto-generated to evaluate variant parametric NoC routers in different terms of reconfigurability for measuring their throughput and average latency. A scalable and portable Universal Verification Methodology (UVM) environment is proposed to support the hardware acceleration using the Testbench-Xpress (TBX) technology for network congestion-aware and bus routing failures detection. Experimental results have been applied on several case studies to demonstrate and asses the validity of the proposed framework of evaluating configurable and different NoC architectures obtain results indicate speedup performance gain in the order of 40X over software simulators.