FPGA Implementation of a Fuzzy Rule Based Contrast Enhancement System for Real Time Applications

The present paper describes a pipeline digital architecture of a fuzzy rule base grayscale image contrast enhancement system. The proposed system uses a zero order Takagi-Sugeno fuzzy model, adapted to avoid the division operation in the deffuzification block and also to reduce the computational requirements for the fuzzification block. The digital architecture is optimized to benefit from the advantages provided by the Xilinx DSP48E2 slice in terms of speed and logic resource consumption. The design has been synthesized and tested on a Xilinx FPGA device and the reported results confirm its viability to be embedded in real time application systems. Also, the functionality of the proposed system was tested on a set of low contrast images, illustrating heavy traffic conditions.