A 239-315 GHz CMOS Frequency Doubler Designed by Using a Small-Signal Harmonic Model

In order to realize a wideband frequency multiplier at terahertz frequencies, iterative optimization of circuit parameters is necessary. However, iterative execution of nonlinear simulation takes a prohibitively long time. We present a small-signal harmonic model, which is equivalent to using only the dominant components of a full set of X-parameters, to solve the problem. It is a simple but accurate nonlinear model suitable for obtaining the frequency response. A 300-GHz frequency doubler with an eight-stage driver amplifier is designed by using the technique. The frequency doubler is fabricated using a 40-nm CMOS process. It achieves a 3-dB bandwidth of 76 GHz from 239 to 315 GHz and a maximum output power of -10 dBm.