A Sub-mW Fractional- ${N}$ ADPLL With FOM of −246 dB for IoT Applications

This paper presents a sub-mW fractional-N all-digital phase-locked loop (ADPLL) with scalable power consumption, which achieves an figure of merit (FOM) of -246 dB. The proposed 10-b ultralow-power isolated constant-slope digital-to-time converter (DTC) achieves a 580-fs resolution and a measured integral nonlinearity (INL) of 870 fs with 0.14-mW power consumption at 52 MS/s. A narrow-range time amplifier (TA)-time-to-digital converter (TDC) with gain calibration minimizes both the in-band phase noise degradation and the loop-bandwidth variation. In addition, a coarse-DPLL is introduced with dead-zone function, which reduces the phase lock time to 4.2 μs at a 13-MHz frequency error. The coarse-DPLL monitors large frequency and phase jump in the background while consuming almost zero power. In an ultralow power mode, the proposed fractional-N ADPLL consumes a 0.65-mW power with a 26-MHz reference. A rms jitter of 1.00 ps and -50-dBc in-band fractional spur are achieved with a -242-dB FOM. In high-performance mode, a reference doubler is utilized, the jitter and spurs can be improved to 535 fs and -56 dBc, respectively, while consuming 0.98 mW. The proposed ADPLL with scalable power and jitter performance can be utilized for Internet-of-Things (IoT) applications, such as Bluetooth low energy (BLE) and Wi-Fi networks.