Strain Distribution Induced in SOI Photonic Substrate by Through Silicon via Using Advanced Scanning X-Ray Nano-Diffraction

In 3-D integration, dice are vertically interconnected with through silicon via (TSV), which consist of holes etched in a thinned silicon substrate and filled with copper. This process induces thermal strain in surrounding silicon. New trends in 3-D integration imply the fabrication of Si photonic devices like waveguides in silicon-on-insulator (SOI) substrates containing TSVs. Thus, a quantitative analysis of strain in active areas around TSVs is mandatory. In this paper, the strain induced by the TSVs in both the bulk silicon and the SOI layer was investigated by using advanced scanning X-ray nano-diffraction. The crystallographic orientation offset between the separated silicon areas allows decorrelation of the strain in the Si layer of the SOI and Si substrate. Using synchrotron radiation, 2-D quicK continuous mapping of the strain in a region of 50 μm × 50 μm with 500 nm spatial resolution was performed around a single TSV at room temperature and during in-situ annealing at 460 °C. The strain field induced by the TSV appears negligible in both silicon areas. The effect of in-situ annealing on the strain distribution is surprisingly weak. In the SOI active layer, the strain map mimics the surface pattern generated by the photonic devices processed at high temperature in this thin layer.