Exact Multi-Level Benchmark Circuit Generation for Logic Synthesis Evaluation

Logic synthesis is a crucial step in digital integrated circuit design. There are methods for exact synthesis of twolevel design able to handle very large circuits, with hundred of inputs, although of limited usefulness in VLSI circuit and system design. On the other hand, exact multi-level synthesis is a quite complex task, where the majority of algorithms are heuristic. To evaluate and validate new methods, benchmarks are of great importance. In particular, exact benchmarks unlock the possibility to evaluate the effectiveness of synthesis algorithm with respect to the optimal solution. This work proposes a novel method to generate exact multi-level circuits based on reversible logic. The proposed approach is able to build exact benchmark circuits with around 40 millions nodes in short time, acting as the identity function f(x) = x. It means, the most compact circuit corresponds to only wires, without any logic gate instantiation. The proposed work is complementary to other circuit generation approaches, being easily combined to explore particular characteristics of related benchmarks.