Auto-Calibrating TDC for a SoC-FPGA Data Acquisition System

In this paper a FPGA-based delay line TDC architecture is presented, featuring an automated calibration system. We were able to predict and test experimentally the TDC timing properties. They were shown to be related to the fundamental parameters of the used FPGA technology. In particular, the best achievable time resolution of this specific architecture (plain tapped delay line on FPGA) is set by to about 24 ps by the sum of the setup and hold times of the registers in the FPGA.