Thermal and electrical performance for wafer level package

CSP (Chip Size Package) is expected to be widely used in D-RDRAM (Direct Rambus DRAM) for its higher electrical performance as well as in PDA (Personal Digital Assistant) applications for its smaller size and lighter weight. Especially wafer level CSP (WL-CSP) has received great attention from semiconductor industries because of its minimal electrical parasitic parameter and thermal resistance. In this study, the thermal and electrical performance of WL-CSP having a high potential for DRAM applications is compared with that of the current TSOP. The thermal performance of WL-CSP was evaluated by means of a thermal model utilizing Finite Element Method (FEM) and Computational Fluid Dynamics (CFD). The results show the excellent thermal performance of WL-CSP at the range of 0.5-2.0 W of a dissipation power. The AC/DC thermo-electrical performance of 64M SDRAM WL-CSP was investigated under various ambient temperatures. The WL-CSP showed the excellent thermo-electrical performance that its access time was max. 5.5 nsec at 90/spl deg/C at the range of 3.3/spl plusmn/0.3 V of VCC. To evaluate the electrical performance of WL-CSP, we designed the three type of WL-CSP with a different redistribution layer design. Their RLC parameters and AC/DC characteristics are measured and compared with the simulation result in order to verify the validity of the simulation result. This result shows that there is a good agreement between the simulation and measurement, and the WL-CSP has better electrical performance than the TSOP.