Design, modeling and simulation methodology for source synchronous DDR memory subsystems

This paper describes the performance modeling and simulation methodology used to optimize the source synchronous timing equations for the system level interconnects. Actual double data rate (DDR) memory system configurations and timing specifications are used to describe the design methodology. The delay skew budget and noise margin allocation for the various components of the optimization equations are discussed in conjunction with their associated delay skew control techniques. This includes: Driver/receiver circuit design techniques, such as controlled driver's impedance and edge rate and differential receivers; resistive termination schemes; board impedance and crosstalk controlled designs; etc. Finally, design guidelines are given for commercially available DDR SDRAMs designs using double pumped bus transfer rates.