Simplified Design Process for Laboratory Prototype of 3-Ph 3-Level Diode Clamped Inverter

An orderly design method for 3-ph, 3-level diode clamped (DCMLI) voltage source inverter (VSI) is presented in this paper. This inverter produces stepped output voltage waveform from DC input source which nearly approaches to sinusoidal with reduced Harmonic Distortion in the out-put voltage wave compared to 2-level inverter. This paper presents step by step procedure for calculation of ratings of power devices and their losses, design of heat sink required based on moderate switching frequency of 2kHz. Matlab/simulink results for presented in this paper for the same switching frequency i.e. 2kHz.