High Speed Current Mode Threshold Logic Gates

Neurons are the basic building block of biological intelligence in human body. Threshold logic gates represents the mathematical model for artificial neuron. There are several ways in which a threshold logic gate can be implemented. This paper mainly focuses on implementing threshold logic gate in current modelogic. Current mode based design has mainly two parts differential part and sensor part. The delay of the threshold gate is caused due to activation time (differential part) and boosting time(sensor part). A new design, which uses tunnel MOS in current mode implementation, which focuses on differential part to reduce delay is presented. Tunnel MOS based design provide less delay compared to purely CMOS based current mode logic gate implementation. The proposed design is applied in simplest current mode threshold logic, differential current mode threshold logic and dual clock current mode threshold logic. Spice simulation results on different gates implemented using the proposed design outperforms consistently the existing implementations in delay.