Modeling and Tuning of an Improved Delayed-Signal-Cancellation PLL for Microgrid Application

An improved delayed-signal-cancellation (DSC) phase-locked loop (PLL) is proposed for microgrid applications. The conventional DSC-PLL suffers from phase and frequency measurement errors due to a fixed delay operation within the control loop. The source of this error is mathematically analyzed in this paper. The modified DSC-PLL model overcomes the error by using a positive sequence αβ detector and a notch filter. The proposed method not only rejects the double frequency oscillation appearing at the output of the PLL under unbalanced loading conditions but also offers good harmonic rejection with nonlinear loads. The proposed model adds minimal complexity to the existing DSC-PLL. To ensure a fast dynamic response as well as a stable operation, a systematic approach is proposed to design the controller gains and filter parameters. The newly designed PLL is simulated and tested for performance verification purposes.