A 0.135 /spl mu/m/sup 2/ 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM

A 0.135 /spl mu/m/sup 2/ trench-capacitor DRAM cell with a trench-sidewall vertical-channel array device has been fabricated using 150 nm groundrules and optical lithography. This 6F/sup 2/ cell features a novel active area layout, a trench-top-oxide (TTO) isolation between trench capacitor and trench gate, maskless self-aligned buried strap node contact, shallow trench isolation (STI), a self-aligned poly-plug bit contact, and two levels of bitline interconnect, both formed using a W dual-damascene process.