A K=3, 2 Mbps low power turbo decoder for 3/sup rd/ generation W-CDMA systems

This paper presents the design of a K=3, 2 Mbps turbo decoder chip targeted for 3/sup rd/ generation wideband CDMA (W-CDMA) systems. This paper makes two contributions. First, finite precision effects on the decoder performance are analyzed and optimal word-lengths are determined. Second, novel power-down techniques are proposed, with which very high power-down efficiency can be achieved without significant performance degradation. The decoder has been designed and fabricated using a 0.25 /spl mu/m standard cell library. The core size is 2.32 mm/spl times/1.72 mm and contains 300 K transistors.