Non-ideality Analysis of Folding and Interpolating ADC

Some non-ideal factors during circuit design of folding and interpolating analog to digital converter (FIADC) are analyzed and summarized in this paper. Based on Matlab software, a 8 bit classic FIADC has been modeled and effects of these non-ideal factors has been validated such as reference voltage varies which caused by the resistance errors, output voltage offset of the track-hold array with different input voltage and the trade-off between gain and linearity of folders. The simulation data has been analyzed at last. These results can be used to estimate distortion of FIADC and guide the circuit design of FIADCs.