Design of VDD generator circuit for a passive UHF RFID tag in 180nm CMOS

This paper describes the design of a Vdd generator in CMOS technology 180nm circuit at 900Mhz frequency in order to have an output voltage of approximately 1 V, and which must be constant and stable for applications in passive UHF RFID Tag. The aim of this work resides in the optimization of the harvesting recuperation block based on the MOS circuit, which is generally of low consumption, which gives it great interest especially for RFID based information retrieval where the problem of energy is paramount. The layout occupies a small active area of 77μm x 89μm in CMOS 180nm.