A Speed Efficient FIR Filter for Reconfigurable Applications

Finite impulse response (FIR) filters having transpose form structure helps in significant computation saving due to its inherent pipelined nature and ability to support multiple constant multiplications (MCM) technique. But MCM technique is not supported by the direct form FIR filter structure. In transpose form the operand, which is common is multiplied with a set of constant coefficients. Hence in transpose form MCM is more effective than the direct form FIR filter structure. Multipliers have a significant role in the design of FIR filters since multiplication is one of the primary arithmetic operations that every application demands. This paper describes high speed transpose form FIR filter that uses Vedic multiplier which helps the performance improvement of the FIR filter architecture. Here a general multiplier-based transpose form block FIR filter architecture is presented which can be used for reconfigurable applications. This paper also describes the Urdhva Tiryagbhyam Vedic method is more efficient for multiplication as compared to the process of normal multiplication. The proposed structure is coded in Verilog HDL, simulated in Xilinx software and simulation is done in Cadence RTL compiler. From the comparison results it is understood that the proposed structure has 27.6
^%
less delay and 2.45% less area compared to the existing structure of FIR filter that is designed for reconfigurable applications.