A Comparative Analysis on the Power Consumption Due to Carry Input in Adder Architectures

This paper presents a comparative analysis on the dynamic power consumption due to carry input in 11 adder architectures and describes estimation of area and power consumption in the adders. Two empirical equations are proposed for estimating dynamic power consumption due to carry input in the Ripple Carry Adder (RC) and relevance of the proposed empirical equations is established from the results obtained using Xilinx Xpower tool. Power analysis of the remaining 10 adder architectures show application of the proposed empirical equations in estimating effect of carry input. Cadence RTL compiler is used to synthesize the design using 0.18μm TSMC technology. The reported results are used to compare computed area, power and rank the adders in terms of power consumed.