Implementation of AES Employing Systolic Array and Pipelining Approach

Data confidentiality necessitates the need of encryption. AES is a worldwide accepted standard for secure data communication. Here data is encrypted by undergoing several rounds of transformation to obtain cipher text. This paper proposes a novel approach to obtain the matrix value, used in various stages of the architecture, using systolic array and employs pipelining for improved latency and throughput. Using systolic architecture complex multiplication is performed with a simplified approach. For the designing of architecture the programming language used in this paper is Verilog. The behavioral modeling is used to connect various stages of the encryption and decryption process. The synthesis and simulation of entire AES 128-bit Verilog code is done using Xilinx_ISE_12.1 and ISIM Simulator respectively. The device utilization is also depicted for targeted Spartan-3E-1600E FPGA. Thereafter, the experimental results are obtained and compared in terms of resource utilization.