Processor Specific Green Counter Based on HSTL IO Standards Design on 90nm FPGA

In today's world with a specific end goal to broaden the battery life and pick up in term of convey ability, there is dependably an examination hole in low power processor plan. Keeping in mind the end goal to finish low power processor configuration venture, there is have to re-plan every single piece of processor with low power methods. Determination of vitality effective I/O standard is additionally assuming a critical part in vitality proficient outline. In this work, we are utilizing High Speed Transceiver Logic (HSTL). This design is implemented in verilog on Zedboard Zynq evaluation kit using vivado 2016.2 tool. Here, we utilize six diverse HSTL IO Standards. These are: HSTL_I, HSTL_II, HSTL_III, HSTL_III_18, HSTL__III_DCI, and HSTL_II_18. For all these IO standard, we checked our Green Counter design on 1.0GHz, 2.5GHz, 3.5GHz, 3.7GHz, 3.9GHz and 4.0GHz processor frequency. With different frequency scaling, we are optimizing 11.22% I/O power, 79.3% clock power and 100% signal power by running our design with 1GHz frequency. As we increased switched to 4.0GHZ to 1.0GHZ frequency we show there is huge amount power conumption. Among all these HSTL_III_DCI consumes maximum power while HSTL_I consumes minimum.