Limits of SiC MOSFETs' Parameter Deviations for Safe Parallel Operation

This paper presents a numerical method combined with a device simulation model used to analyse the parallel connection of several SiC MOSFET dies. Parallel connection is necessary to achieve the desired current carrying capability of main inverters for xEV-drives. With this method, the effect of asymmetries within the chips' on-state resistance coupled with asymmetries in the threshold voltage is investigated. The investigation result quantifies, to what extent the threshold voltage and the on-state resistance of the chips can vary at the same time, when the output power of the inverter should only be derated by 5 % at most and no single chip in the inverter should be overheated. To achieve this derating limit, the impact of the positive temperature coefficient (PTC) of the output characteristic and the thermal coupling between the paralleled chips is examined.