Keynote Talk: Many-Core SoC in Nanoscale CMOS: Challenges & Opportunities

Many-core SoC designs in scaled CMOS process demand wide dynamic voltage-frequency operating range, spanning multi-threaded high-throughput near-threshold voltage (NTV) to single-threaded burst performance modes, as well as fine-grain multi-voltage design and spatio-temporal power management to deliver maximum performance under stringent thermal and energy constraints. Interconnect scaling bottlenecks, process-voltage-temperature variations and aging-induced degradation pose major challenges going forward. We present key circuit and design techniques for logic, memory and on-die interconnect networks that enable efficient, variation-tolerant and resilient many-core SoC designs in nanoscale CMOS.