A Simulation Study of NBTI Impact on 14-nm Node FinFET Technology for Logic Applications: Device Degradation to Circuit-Level Interaction

A comprehensive simulation flow is demonstrated to assess the negative-bias temperature instability (NBTI) impact on the performance and power of digital logic circuits based on the 14-nm node FinFET technology. Fully calibrated technology computer-aided design simulations are used to determine the preaged and postaged device characteristics; the results are used for calibrating the BSIM-CMG compact model. Standard cell libraries are characterized next, by only threshold voltage shift (ΔV
_T
) and by both ΔV
_T
and subthreshold slope shift (ASS). Various benchmark circuits are synthesized and analyzed, and their timing degradation is compared to ring oscillator results. The consequence of ignoring ASS on off current and static power (P
_static
) is estimated.