Power-performance Trade-offs for Lateral NanoSheets on Ultra-Scaled Standard Cells

In this paper, the performance of standard cells scaled down to 4.5 metal tracks based on Lateral NanoSheets is investigated for 3nm technology node targets using relevant logic benchmarks and power-aware metrics. The cell layout and parasitics in 4.5T cells set strong constraints on the NanoSheets geometry. The optimized NanoSheets could still outperform FinFETs by 9 to 20% frequency depending on circuit context, reaching 3nm node targets. An extra 21% performance improvement is expected with device level boosters enablement.