Strain Optimization in Silicon P-Type Double-Gate MOSFET at 7nm Channel Length

Strain has been proved to be an effective approach to boost CMOS device performances. As channel length being scaled to sub-10nm, strain needs to be carefully optimized with quantum effects fully accounted for. In this work, optimal strain orientation and magnitude are identified for a ultra-thin-body (UTB) silicon double-gate (DG) P-MOSFET at 7nm gate length and 3nm channel thickness. The optimization is based on accurate quantum transport simulations using the nonequilibrium Green’s function (NEGF) approach and strained sixband k·p model. Various confinement and transport crystal orientations, different types of strain, and a range of strain strengths are considered. Device performances such as the ballistic ON-state current (ION) and subthreshold swing (SS) are extracted and compared. Analysis shows strong correlation between strain and source-to-drain tunneling (SDT) effect.