RFIC IP Redesign and Reuse Through Surrogate Based Machine Learning Method

This paper presents an efficient approach for RFIC design optimization and explores the potential to reuse state of the art Intellectual Property(IP) across different technology nodes. This is treated as a transistor circuit level optimization problem. A solution is presented based on Surrogate Model with candidate sample and Nu-Support Vector Machine (SVM) for inductor model fitting. In this paper, two design examples, a 9.6GHz VCO with Inductor Co-Optimization and a 79GHz Mixer, are demonstrated with the proposed design flow and both achieve promising performance results than manual design. The proposed approach can be used in any RF circuit block to help accelerate design automation and IP redesign/reuse.