A 0.5-1.1V 10B Adaptive Bypassing SAR ADC Utilizing Oscillation Cycle Information of VCO-Based Comparator

VCO-based comparators generate both bit decisions as well as oscillation cycle information, whereas the latter has not been exploited in SAR ADCs. This work presents a SAR ADC using oscillation cycle as the thresholds for multiple bypass windows, which improves energy efficiency. PVT-induced variations are compensated by adaptive windowing. The implemented 40nm ADC is robust under wide supply voltages ranging 0.5-1.1V with 9.71b peak ENOB at 1.1V and 2.4fJ/c.-s. lowest FoM at 0.5V without any tuning.