A 14 µM × 26 µM 20-GB/S 3-MW CDR Circuit with High Jitter Tolerance

A full-rate CDR loop employs a 3-stage ring VCO, a master-slave passive sampler as both a phase detector and a filter, and a new flipflop to achieve a bandwidth of 170 MHz. Implemented in 45-nm CMOS technology, the circuit exhibits a jitter tolerance of 2 UI at 5 MHz and a recovered clock jitter of 340 fs with 2
⁷
-1 PRBS.