Energy Efficient Adiabatic FRAM with 0.99 PJ/Bit Write for IoT Applications

Low access energy embedded non-volatile memory is critical for low power sensing systems. This paper proposes a charge-recycling FRAM design that uses resonance between the FRAM array capacitance and an off-chip inductor to perform both write and read functions. In 130 nm, the 256×80 FRAM increases energy efficiency by 3× compared to standard operation, achieves 0.99pJ/bit write energy, 0.4pJ/bit read energy and 102Mbps at 1V.