A Thick Cu Layer Buried in Si Interposer Backside for Global Power Routing

A layer of thick Cu metal is buried in the backside of a Si interposer and provides low resistivity and high capacitance for high-performance on-die power delivery networks (PDNs). The backside buried metal (BBM) layer can be as thick as
$10 ~\mu \text{m}$
or even larger, and the stripes formed on the layer for interleaving power supply (
$V_{\mathrm {DD}}$
) and ground (
$V_{\mathrm {SS}}$
) wirings have large cross-sectional areas. The process flow developed for BBM is fully compatible with via-last type through-silicon via manufacturing. The Si interposer with BBM is stacked over an integrated circuit (IC) chip for improving PDN performance and suppressing power supply noise, as an over-the-top Si interposer (OVTT-SiIP). A test device of 65-nm CMOS digital IC chip and OVTT-SiIP was manufactured. The noise suppression ratio of 59.6% by the OVTT-SiIP technology is demonstrated by simulation with a full-chip PDN equivalent circuit network model and consistent with 49.7% by measurements on the test device with on-chip power noise monitoring function.