A sub 10 pJ/Cycle Over a 2 to 200 MHz Performance Range RISC- V Microprocessor in 28 nm FDSOI

This work presents a near-threshold microprocessor implementation that aims for ultra-high energy-efficiency, while providing MHz performances over a 100x frequency range. This allows the processor to target a wide range of applications and to provide edge computing capabilities to IoT-devices. The RISC-V IM32 ISA is implemented in 28 nm FDSOI technology. FDSOI's body-biasing capabilities are explored and result in performance specific energy optimization possibilities. Furthermore, near-threshold libraries that are based on the original technology's super-threshold standard-cells, allow for a swift implementation of the processor without the need to design a custom low-voltage standard-cell set. Measurements show that the processor core breaks the 10 pJ/ cycle energy barrier over a frequency range from 2-200 MHz. The design remains functional down to 250mV with a MEP of 4.18pJ/cycle at 21.5MHz (380 mV). The 2×32 kB on-chip SRAM consumes between 4.49 pJ /cycle and 9.58 pJ/cycle while operating at 0.5 V.