An Enhanced Algorithm for Variable Reordering in Binary Decision Diagrams

The data structures which have a significant role for representing and manipulating Boolean functions in VLSI Design Automation are Reduced Ordered Binary Decision Diagrams (ROBDDs). Boolean function manipulation is highly efficient at solving many problems in wide array of fields including digital logic design, intelligent systems along with combinatorial problem. Therefore, binary decision diagrams (BDDs) or ordered binary decision diagrams (OBDDs) have been shown to be a powerful tool in solving problems in the above areas. The variable ordering largely influences the size of the BDD, varying from the linear to exponential. Our paper outlines an enhanced variable ordering algorithm which shall be capable to produce the minimum number of nodes for a given Reduced Ordered Binary Decision Diagrams (ROBDD). The efficiency of the proposed technique is illustrated on a number of benchmarks and compared to existing algorithms to prove its validity for use.