A Novel Low-Complexity VLSI Architecture for an EEG Feature Extraction Platform

This paper presents a novel low-complexity VLSI architecture for an EEG Feature Extraction Platform for wearable health monitoring systems. It integrates a processing core unit, preprocessing FIR filter block and an FFT accelerator. The platform supports 8 scalp EEG channels and it can be scaled up to 16 or 32 EEG channels. In this paper, we analyze several architectural optimizations for hardware implementation of features such as Power Spectral Density, Discrete Wavelet Transform, Autoregression etc. The proposed architecture is easily scalable to new feature extractors. An FFT accelerator is proposed to improve the flexibility of the platform. We provide a comparison with software models for each feature extractor and also validate the platform by implementing a seizure detection algorithm on CHB-MIT Scalp EEG database with an accuracy of over 95%.