A case for multiple and parallel RRAMs as synaptic model for training SNNs

To enable a dense integration of model synapses in a spiking neural networks (SNN) hardware, various nanoscale devices are being considered. Such devices, besides exhibiting spike-timing dependent plasticity (STDP), need to be highly scalable, have a large endurance and require low energy for transitioning between states. In this work, first, we introduce and empirically determine two new specifications for a resistive random-access memory (RRAM) based synapse: number of conductance levels per synapse and learning-rate. To the best of our knowledge, there are no RRAMs that meet the latter specification. As a solution, we propose the use of multiple RRAMs in parallel within a synapse. While synaptic reading, all RRAMs are simultaneously read and for each synaptic conductance-change event, the mechanism for conductance STDP is initiated on only one RRAM, randomly picked from the set. Second, to validate our solution, we experimentally demonstrate STDP of conductance of a Pr
_0.7
Ca
_0.3
MnO
₃
(PCMO)-RRAM and then show that due to a large learning-rate, a single PCMO-RRAM fails to model a synapse in the training of an SNN. As anticipated, network training improved as more PCMO-RRAMs were added to the synapse. Fourth, we discuss circuit-requirements for implementing such a scheme, to conclude that the requirements are within bounds. Thus, our work presents specifications for synaptic devices in trainable SNNs, indicates the shortcomings of state-of-art synaptic contenders, and provides a solution to extrinsically meet the specifications and discusses the peripheral circuitry that implements the solution.