A voltage controlled resistor in CMOS technology using bisection of the voltage range

A voltage controlled linear, non-grounded resistor in CMOS technology is presented. It is based on the conversion of the transconductance of the MOSFET in the saturated region to the drain-to-source resistance of the MOSFET in the nonsaturated region. A new approach in the realization of the known linearization technique is applied. Bisection of the input voltage of the controlled resistor is involved by this technique. Simulation results have shown a linearity error less than 0.58% of full scale in the 0 V to 7 V input voltage range.